ASIC Verification Engineer

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.

Join the Cisco Common ASIC Group, a team responsible for developing the ASICs at the heart of Cisco's next-generation switching systems. These ASICs are becoming more general and programmable, moving beyond traditional high-speed packet forwarding. You will work with Cisco’s best-in-class switching solution team, driving the integration of Nexus systems and ACI with software like OpenStack, Docker, and Open vSwitch, to empower our customers in building multi-tenant clouds. Every time you access the Internet, chances are, your data has passed through one of our switches.

As an ASIC Verification Engineer, you will be a vital part of the team developing and upgrading various test benches and contributing to different aspects of verification infrastructure. You will collaborate closely with design and hardware teams to verify ASICs across simulation, emulation, and during ASIC bring-up. Your responsibilities will include:

• Driving existing projects and engaging in new development for next-generation switching systems.
• Developing and upgrading test benches, including components like drivers, monitors, and sequences.
• Maintaining existing test benches for both block-level and cluster-level verification.
• Upgrading test benches to accommodate new features and design changes.
• Performing end-to-end verification of various design blocks.
• Developing comprehensive test plans and cover points.
• Upgrading and updating configuration/reset sequences (APIs).
• Collaborating with designers and verification engineers for cross-block verification.
• Writing tests and debugging regressions to ensure robust ASIC functionality.
• Contributing to top-level verification efforts.
• Actively participating in emulation testing efforts.

• Master’s degree in Electrical & Electronics or Computer Engineering with 2 or 3 years of experience in Design Verification.
• Proficiency in functional coverage and constrained random Design Verification (DV) environments.
• Ability to debug issues independently and efficiently.
• Hands-on and deep understanding of System Verilog and UVM methodology.

• Ability to construct testbenches including scoreboards, agents, sequencers, and monitors.
• Basic scripting experience (Python, Perl, shell programming).
• Nice to have C, C++ programming and debugging skills.
• Good written and verbal communication skills.
• Collaborative and team-focused, with a strong drive to learn and grow within the field

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you.