Scan/ATPG Methodology Development Engineer

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Qualcomm’s Global CAD Organization is seeking a DFT CAD/Methodology Development Engineer to develop DFT methodologies for Qualcomm products in next-generation semiconductor process nodes. In this role, you will be part of a global technical team collaborating across SoC Design, DFT, Product & Test, Diagnostics, and EDA tool partners to deliver world-class DFT solutions.

Key Responsibilities

• Develop, deploy, support DFT flows as part of the DFT CAD team, working closely with DFT teams and EDA vendors worldwide.
• Evaluate and implement new methodologies for Scan insertion, ATPG, pattern simulations; assess new tools/features; design experiments (DoEs) in collaboration with internal teams and external partners.
• Create optimized methodologies to reduce DFT implementation effort, improve test quality, lower test cost, shorten cycle time, and accelerate pattern simulation runtimes.

NOTE: This is DFT methodology, flow development role and NOT DFT implementation/execution role.

Qualifications/Experience

• Bachelor’s or Master’s degree (BE/B.Tech, ME/M.Tech, MS) in Electrical, Electronics, or Computer Science Engineering.
• 1–2 years of demonstrated experience in VLSI EDA/CAD methodology development, specifically in DFT, Scan/ATPG, and/or MBIST.

Skills Required

• Strong technical knowledge of DFT concepts including Scan, Compression, ATPG, pattern simulation, diagnosis.
• Hands-on experience with DFT EDA tools for Scan insertion, ATPG (e.g., Tessent, TestMax)
• Proficiency in scripting languages such as TCL (for EDA tools) and Python.
• Familiarity with DFT execution workflows.
• Understanding of standard software development processes including configuration management, QA, release, and support.
• Ability to collaborate effectively with global teams in a fast-paced, dynamic environment.
• Detail-oriented, adaptable, and a strong team player with the ability to multi-task.

Keywords:

DFT, ATPG, Scan, VLSI Test, Tessent, TetraMAX, TestMax, Modus

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